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Address review: drop unused bti c landing pads, fix rationale comment
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This commit is contained in:
weaselbot
2026-08-03 09:17:28 -04:00
parent d040ed63a4
commit e02dd41f74
1 changed files with 11 additions and 9 deletions
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simd_aarch64.S
+11 -9
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@@ -1,8 +1,8 @@
// SIMD operations on potentially-indeterminate Node16::index[16] bytes. // SIMD operations on potentially-indeterminate Node16::index[16] bytes.
// Written in assembly so msan doesn't track the loads, and so that loading // Written in assembly because loading and operating on indeterminate values
// and operating on indeterminate values is well-defined (unlike C++). The // is undefined behavior in C++ ([basic.indet]) but well-defined in assembly.
// caller is responsible for masking the returned bitfield to [0, numChildren) // The caller is responsible for masking the returned bitfield to
// before using it. // [0, numChildren) before using it.
// //
// Unlike x86-64 (which has pmovmskb), AArch64 has no single instruction that // Unlike x86-64 (which has pmovmskb), AArch64 has no single instruction that
// produces a 1-bit-per-byte mask. Each function therefore returns a 64-bit // produces a 1-bit-per-byte mask. Each function therefore returns a 64-bit
@@ -16,6 +16,10 @@
// w1 = uint8_t key (find_eq_16, find_ge_16) // w1 = uint8_t key (find_eq_16, find_ge_16)
// w1 = uint8_t begin (mask_in_range_16) // w1 = uint8_t begin (mask_in_range_16)
// w2 = uint8_t end (mask_in_range_16) // w2 = uint8_t end (mask_in_range_16)
//
// These functions are only ever called directly (never indirectly), so they
// do not need BTI landing pads; the object is still marked BTI/PAC/GCS-aware
// below so a -z force-bti link keeps BTI enabled for the whole binary.
.text .text
@@ -24,7 +28,6 @@
.globl find_eq_16 .globl find_eq_16
.type find_eq_16, %function .type find_eq_16, %function
find_eq_16: find_eq_16:
hint 34 // bti c
dup v1.16b, w1 // broadcast key dup v1.16b, w1 // broadcast key
ldr q0, [x0] // load 16 bytes (may be indeterminate) ldr q0, [x0] // load 16 bytes (may be indeterminate)
cmeq v0.16b, v0.16b, v1.16b // 0xff for each match cmeq v0.16b, v0.16b, v1.16b // 0xff for each match
@@ -39,7 +42,6 @@ find_eq_16:
.globl find_ge_16 .globl find_ge_16
.type find_ge_16, %function .type find_ge_16, %function
find_ge_16: find_ge_16:
hint 34 // bti c
dup v1.16b, w1 // broadcast child dup v1.16b, w1 // broadcast child
ldr q0, [x0] // load 16 bytes ldr q0, [x0] // load 16 bytes
cmhs v0.16b, v0.16b, v1.16b // 0xff where idx[i] >= child (unsigned) cmhs v0.16b, v0.16b, v1.16b // 0xff where idx[i] >= child (unsigned)
@@ -56,7 +58,6 @@ find_ge_16:
.globl mask_in_range_16 .globl mask_in_range_16
.type mask_in_range_16, %function .type mask_in_range_16, %function
mask_in_range_16: mask_in_range_16:
hint 34 // bti c
dup v1.16b, w1 // broadcast begin dup v1.16b, w1 // broadcast begin
dup v2.16b, w2 // broadcast end dup v2.16b, w2 // broadcast end
ldr q0, [x0] // load 16 bytes ldr q0, [x0] // load 16 bytes
@@ -71,8 +72,9 @@ mask_in_range_16:
// Declare AArch64 branch-protection compatibility, matching what the // Declare AArch64 branch-protection compatibility, matching what the
// compiler emits for -mbranch-protection=standard (BTI + PAC + GCS). This // compiler emits for -mbranch-protection=standard (BTI + PAC + GCS). This
// keeps the object indistinguishable from C/C++ translation units for // keeps the object indistinguishable from C/C++ translation units for
// linkers enforcing BTI (-z force-bti); the functions above only use // linkers enforcing BTI (-z force-bti). The functions above are only ever
// `bti c` and no stack, so PAC/GCS compatibility holds trivially. // called directly, so they need no BTI landing pads; PAC/GCS compatibility
// holds trivially since they use no stack.
.aeabi_subsection aeabi_feature_and_bits, optional, ULEB128 .aeabi_subsection aeabi_feature_and_bits, optional, ULEB128
.aeabi_attribute Tag_Feature_BTI, 1 .aeabi_attribute Tag_Feature_BTI, 1