weaselab/weaseldb
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Remove misleading comment

Browse Source
This commit is contained in:
Andrew Noyes
2025-08-21 15:31:15 -04:00
parent 21ac6c6efa
commit 810b5e006d
1 changed files with 0 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/ThreadPipeline.h
View File

@@ -36,8 +36,6 @@
// //
// Memory Model: // Memory Model:
// - Ring buffer size must be power of 2 for efficient masking // - Ring buffer size must be power of 2 for efficient masking
// - Uses 64-bit indices to avoid ABA problems (indices never repeat until
// uint32_t overflow)
// - Actual ring slots accessed via: index & (slotCount - 1) // - Actual ring slots accessed via: index & (slotCount - 1)
// - 128-byte aligned atomics prevent false sharing between CPU cache lines // - 128-byte aligned atomics prevent false sharing between CPU cache lines
// //