Commit Graph
828 Commits
Author SHA1 Message Date
andrew ed67486077 Reordering seems to improve codegen 2024-09-23 15:28:51 -07:00
andrew b376f6fdd5 WIP 2024-09-23 15:11:48 -07:00
andrew 6de63dd3fe Use preserve_none and put continuation array in CheckAll 2024-09-23 14:53:16 -07:00
andrew 3e5f13bf54 WIP - tests pass 2024-09-23 13:32:56 -07:00
andrew e7e1d1f7f5 Add tail-call based interleaving approach 2024-09-23 12:52:30 -07:00
andrew 442658e983 Target ~1GB memory usage in server bench 2024-09-21 14:28:15 -07:00
andrew 26f602215e Accentuate cache misses for point reads in server_bench 2024-09-14 22:42:40 -07:00
andrew 98236f81cb Add missing __builtin_prefetch 2024-09-14 22:41:58 -07:00
andrew 3593b72880 Disallow checking SIM_CACHE_MISSES=1 2024-09-10 22:23:37 -07:00
andrew 814aac4ea7 Experiment with causing cache misses 2024-09-10 22:06:00 -07:00
andrew 0550fa0016 Add "iter" state 2024-09-10 17:22:10 -07:00
andrew fe5cfb0336 Remove redundant cast 2024-09-10 17:06:45 -07:00
andrew 82203515a0 check_point_read_state_machine::down_left_spine 2024-09-10 17:05:09 -07:00
andrew 465372c734 Scaffolding to prepare for interleaving checks 2024-09-10 16:10:57 -07:00
andrew 867136ff1b Return pointer to next function 2024-09-09 21:59:49 -07:00
andrew 4b8f7320d3 Call function pointer in job 2024-09-09 21:00:31 -07:00
andrew 6628092384 Tinker with interleaveBoundedCyclicList 2024-09-09 20:25:40 -07:00
andrew a0a4f1afea Only compile nanobench once 2024-09-09 20:10:55 -07:00
andrew ca479c03ce Induce a cache miss in interleaving test 2024-09-09 17:55:35 -07:00
andrew 0a2e133ab9 Add InterleavingTest to explore #5 2024-09-09 17:27:58 -07:00
andrew b0b31419b0 Remove vestigial emscripten from cmake 2024-09-06 20:29:59 -07:00
andrew 5c0cc1edf5 Add longestCommonPrefix bench 2024-09-05 16:30:58 -07:00
andrew de47aa53b0 Add to corpus 2024-09-05 16:24:41 -07:00
andrew 56893f9702 Update stale comments 2024-09-05 10:06:02 -07:00
andrew e2234be10f Update README.md 2024-09-04 13:08:20 -07:00
andrew ce853680f2 Finish checkRangeRightSide conversion 2024-09-04 12:36:43 -07:00
andrew 5c39c1d64f CheckRangeRightSide conversion WIP 2024-09-04 12:25:16 -07:00
andrew 55b73c8ddb Convert CheckRangeRightSide WIP 2024-09-04 12:22:36 -07:00
andrew b9503f8258 Converting CheckRangeRightSide WIP 2024-09-04 12:19:53 -07:00
andrew c4c4531bd3 Simplify 2024-09-04 12:12:54 -07:00
andrew 2037d37c66 checkRangeLeftSide 2024-09-04 12:11:16 -07:00
andrew 6fe6a244af Get CheckRangeLeftSide closer, WIP 2024-09-04 12:08:16 -07:00
andrew 8a4b370e2a Make CheckRange{Left,Right}Side into normal functions, WIP 2024-09-04 12:04:58 -07:00
andrew 394f09f9fb WIP adding metrics to skiplist 2024-08-30 16:06:43 -07:00
andrew 5e06a30357 Add optional microbenchmarks for rezero/scan avx512 2024-08-29 12:12:24 -07:00
andrew cb6e4292f2 Add to corpus 2024-08-26 14:33:16 -07:00
andrew 154a48ded0 Bump version 2024-08-26 14:25:13 -07:00
andrew c11b4714b5 Check more preconditions in Debug mode v0.0.13 2024-08-26 12:43:07 -07:00
andrew bc13094406 Don't violate precondition in test_conflict_set.py 2024-08-26 11:13:16 -07:00
andrew c9d742b696 Make explicit the precondition that versions must be <= latest version 2024-08-24 13:43:39 -07:00
andrew 795ae7cb01 Internal.h doesn't need to include <vector> 2024-08-24 10:38:07 -07:00
andrew 849e2d3e5c Remove unused code 2024-08-22 22:31:36 -07:00
andrew 1560037680 Remove unused struct 2024-08-22 17:55:54 -07:00
andrew 764c31bbc8 Run skip list gc at 200% entry insertion rate 2024-08-22 17:26:08 -07:00
andrew ee3361952a Use better rng in skip list
low bits of lcg have low periods
2024-08-22 17:00:15 -07:00
andrew 8a04e57353 Add to corpus 2024-08-22 16:52:33 -07:00
andrew 7f86fdee66 Test 64 bit versions
Keep 32 bit versions the default though
2024-08-21 14:00:00 -07:00
andrew 442755d0a6 Update implementation notes
This doesn't really capture the complexity, but at least it's more
accurate
2024-08-21 14:00:00 -07:00
andrew e15b3bb137 Bump version 2024-08-20 16:58:39 -07:00
andrew 311794c37e Update GCOVR annotations now that jenkins agent has avx512 v0.0.12 2024-08-20 16:34:27 -07:00